Current-mode logic (CML) drivers are often employed as a key component of a transmitter in both ReDriver/ReTimer and Serializer/Deserializer (SERDES) applications for high speed serial links. These drivers more often than not provide the capability of pre-emphasizing a signal being transmitted to compensate for a frequency-dependent loss of the channel. This type of circuit consists of one main tap driver and one post tap driver, both of which typically are implemented as CML drivers. The post tap driver transmits data that is delayed from the main tap path data by one unit interval (UI) which is the inverse of the data rate.
This delayed-by-one-UI data is typically achieved with the help of an on-chip high speed clock that runs at a frequency which corresponds to the data rate. However, in the case where such a clock is not present, such as in a low cost, low power ReDriver application, additional effort is required to implement this delay element for the post tap driver. Furthermore, modern transceivers are often designed to support multiple standards and multiple data rates. For example, the delay provided by the delay cell needs to be programmable, i.e., if the data rate is 2.5 Gbps, the delay provided by the delay cell needs to be 400 ps; if the data rate is 6.25 Gbps, the delay needs to be 160 ps.
Another constraint for the delay cell is that the delay variation over PVT corners needs to be well controlled. If, on the transmitter side, the delay produced by the delay cell differs too much across corners from the nominal value determined by the data rate, it can greatly degrade the performance of receiver equalization.
DC offset is another problem faced by any chain-based delay generation circuit. With the scaling down of modern CMOS technology, the device geometric size is considerably shrinking which makes device mismatch more significant as it is inversely proportional to the square root of device area. A multi-stage delay chain can make matters worse as the input referred DC offset will be amplified by a chain of amplifiers to the extent that the resulting output referred offset could be comparable to data signal levels.
Conventional CMOS inverter based chain delay cell is the most common way of generating a delay but it usually has at least +/−50% variation over PVT corners without any sort of complicated calibration which makes it undesirable for this application. Another drawback is that the main signal flavor is mostly kept as CML in drivers so if the delay cell is CMOS based, extra circuits will be needed to convert signals back and forth between CML and CMOS.
Another attempted solution is to use multiple stage, cascaded conventional CML amplifiers. The concept is similar to that of an inverter chain delay solution while the difference is the delay variation over PVT corners now mainly comes from poly resistor and device/parasitic capacitance on the output node which usually varies to a lesser extent. Problems with this approach include the requirement of a relatively large number of stages to produce the UI delay for lower data rates. This translates to greater power consumption. Cascading more stages together also lowers the bandwidth of the entire delay chain which would introduce inter-symbol interference (ISI). Another problem with this approach includes the lack of programmability of delay values to support multiple data rates.
Conventional methods for dealing with amplifier chain offset include making the key transistors very large to achieve a decreased incidence of mismatch. This approach could either slow down the amplifier or increase the power consumption of the amplifier chain. Another known method is to perform a one-time calibration. One state machine will short both differential inputs of the amplifier chain and add a compensation force until the differential output voltage equals zero. The concept includes adding a calibration force against intrinsic device mismatch to re-gain the DC differential balance. One problem with this approach is that the calibration force required is frequency-dependent. Such a DC-wise calibration can have significant residue of the offset and can degrade the performance. It also does not track the change in offset introduced by PVT change.